-------------------------------------------------------------------------------
-- Archivo:                      hazards_unit.vhdl
-- Fecha de creación:            18/01/2011
-- Ultima fecha de modificacion: 30/01/2011
-- Diseñador:                    Samantha Gamboa.
-- Diseño:                       hazards_unit
-- Propósito:                    Unidad que chequea si existen dependencias   
--                               entre las instrucciones que estan en la cola
--				 de instrucciones del procesador vectorial. 
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

--Diseño de la entidad (caja negra)
  entity hazards_unit is
  port(
    --ENTRADAS
    CURR_INST_i : in std_logic_vector(11 downto 0);
    NEXT_INST_i : in std_logic_vector(11 downto 0);
    --SALIDAS:
    --Bit que indica dependencia de datos o peligros estructurales
    HAZARD_o	: out std_logic
    );
end hazards_unit;
  
--Diseño  de especificacion de comportamiento
architecture structural of hazards_unit is 
    
	--Declaraciones
	component comparation_unit 
	port(
   		CURR_INST_i : in std_logic_vector(11 downto 0);
   		NEXT_INST_i : in std_logic_vector(11 downto 0);
		EQ45_45_o : out std_logic;
		EQ45_67_o : out std_logic;
		EQ45_89_o : out std_logic;
		EQ67_45_o : out std_logic;
		EQ67_67_o : out std_logic;
		EQ67_89_o : out std_logic;
		EQ89_45_o : out std_logic;
		EQ89_67_o : out std_logic;
		EQ89_89_o : out std_logic
	);
	end component;

	component dependency_selection 
	port(
   		CURR_OP_i : in std_logic_vector(3 downto 0);
   		NEXT_OP_i : in std_logic_vector(3 downto 0);
		EQ45_45_i : in std_logic;
		EQ45_67_i : in std_logic;
		EQ45_89_i : in std_logic;
		EQ67_45_i : in std_logic;
		EQ67_67_i : in std_logic;
		EQ67_89_i : in std_logic;
		EQ89_45_i : in std_logic;
		EQ89_67_i : in std_logic;
		EQ89_89_i : in std_logic;
		HAZARD_o : out std_logic
	); 
	end component;

	signal equal45_45_wire: std_logic;
	signal equal45_67_wire: std_logic;
	signal equal45_89_wire: std_logic;
	signal equal67_45_wire: std_logic;
	signal equal67_67_wire: std_logic;
	signal equal67_89_wire: std_logic;
	signal equal89_45_wire: std_logic;
	signal equal89_67_wire: std_logic;
	signal equal89_89_wire: std_logic;
	signal curr_ins : std_logic_vector(11 downto 0);
	signal next_ins : std_logic_vector(11 downto 0);
	signal curr_op : std_logic_vector(3 downto 0);
	signal next_op : std_logic_vector(3 downto 0);
	signal dep_out: std_logic;

begin 
--Comportamiento	
	curr_ins <= CURR_INST_i;
	next_ins <= NEXT_INST_i;

	curr_op <= CURR_INST_i(11 downto 8);
	next_op <= NEXT_INST_i(11 downto 8);
	
	CMP_U : comparation_unit
	port map(
   		CURR_INST_i => curr_ins,
 		NEXT_INST_i => next_ins,
		EQ45_45_o =>equal45_45_wire,
		EQ45_67_o =>equal45_67_wire,
		EQ45_89_o =>equal45_89_wire,
		EQ67_45_o =>equal67_45_wire,
		EQ67_67_o =>equal67_67_wire,
		EQ67_89_o =>equal67_89_wire,
		EQ89_45_o =>equal89_45_wire,
		EQ89_67_o =>equal89_67_wire,
		EQ89_89_o =>equal89_89_wire
	);

	DEP_SEL : dependency_selection
	port map(
		CURR_OP_i =>curr_op,
  		NEXT_OP_i =>next_op,
		EQ45_45_i =>equal45_45_wire,
		EQ45_67_i =>equal45_67_wire,
		EQ45_89_i =>equal45_89_wire,
		EQ67_45_i =>equal67_45_wire,
		EQ67_67_i =>equal67_67_wire,
		EQ67_89_i =>equal67_89_wire,
		EQ89_45_i =>equal89_45_wire,
		EQ89_67_i =>equal89_67_wire,
		EQ89_89_i =>equal89_89_wire,
		HAZARD_o =>dep_out
	);

	HAZARD_o <=dep_out;	

end structural;



